library ieee;
use ieee.std_logic_1164.all;

entity dffr is
port(d,clk,r:in std_logic;
	q:out std_logic);
	
end dffr;


architecture bhv of dffr is
begin

process(clk,r)
	begin
	if (r='1') then
		q<='0';
	elsif (clk'event and clk='1') then
		q<=d;
	end if;
end process;

end bhv;